FPGA Design Engineer

22k - 29k PLN/ mies.UoP
SeniorFull-time·Umowa o pracę
#383098·Dodano dziś·0
Źródło: justjoin.it
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Tech Stack / Keywords

FPGA

Firma i stanowisko

Resquant is a rapidly growing deep-tech startup focused on next-generation chip security and quantum-resistant cryptography solutions for dual-use and high-security applications. We develop advanced hardware security technologies designed to address emerging threats in post-quantum computing environments, working at the intersection of cryptography, semiconductor engineering, and secure system architecture. We are building a team of highly skilled engineers passionate about cutting-edge FPGA and ASIC development, secure hardware design, and innovative defense-grade technologies.

Wymagania

  • Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
  • 8+ years of hands-on experience in FPGA design and development for Senior-level.
  • Proficient in any VHDL, Verilog, or SystemVerilog for RTL design.
  • Knowledge of ASIC design process.
  • Experience with timing analysis, synthesis, and implementation workflows.
  • Experience with high-speed interfaces and protocols such as PCIe, Ethernet, AXI.
  • Knowledge of system integration, including embedded processors.
  • Ability to work independently or strong cooperation skills to work within a cross-functional team.
  • Strong problem-solving and analytical thinking skills.
  • EU citizenship.

Nice to have:

  • Knowledge in the field of cryptography.
  • Experience in side-channel attacks and countermeasures.
  • Experience with space technologies and requirements.
  • EU/NATO security clearance.

Obowiązki

  • Developing and implementing RTL at block and subsystem level for quantum resistant cryptographic algorithms and cryptographic processors.
  • Defining micro-architecture, performing simulations, and synthesizing digital design.
  • Top-level architecture modeling and integration with 3rd party IP (e.g. RISC-V).
  • Tuning up countermeasures against side-channel attacks.
  • Preparing input for verification environment for FPGAs and ASICs.
  • Participation in certification and technical documentation development.
  • Cooperation with ASIC backend team.

Benefity

  • Full time Senior and Mid positions.
  • Participation in projects aimed at providing backbone for chip security for dual-use markets.
  • Flexible working hours.
  • Ability to work remotely (Hybrid/Full).
  • Equity options.
  • Broad Technical Ownership.
  • Innovation and Cutting-Edge Projects.
  • Opportunity to attend closed events with military representatives.
Elastyczne godziny

Inne informacje

EU citizenship required.

Resquant Sp. z o.o.

Resquant Sp. z o.o.

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