DFT Lead (Semiconductors)

Capgemini is an AI-powered global business and technology transformation partner with nearly 60 years of heritage and over 420,000 team members in more than 50 countries. They deliver end-to-end services and solutions across strategy, technology, design, engineering and business operations.

• 6+ years of hands-on experience with DFT and test flows using commercial EDA tools for large and complex SoCs.
• Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, scan compression, IEEE 1500 Std., and MBIST/LBIST.
• Experience with major EDA providers such as Synopsys DFT Compiler, Tetramax, VCS, Tessent, and Modus/Encounter tool suite.
• Experience with RTL simulation, synthesis, linting, CDC and RDC checks, STA, DFT, and quality metrics is a plus.
• Hands-on experience with Perl, Tcl, and Python scripting.
• Excellent analytical and problem-solving skills.

• Implement DFT inline with existing test methodology for advanced process nodes.
• Perform top and/or block-level DFT insertion including scan compression, (i)JTAG, ATPG, pattern validation/simulation, MBIST/LBIST.
• Collaborate closely with physical design team to resolve timing constraints and issues.
• Verify DFT circuitry, interface with other components/IPs, and debug timing simulation issues.
• Debug and improve key DFT KPIs such as test coverage and pattern efficiency.
• Perform hierarchical retargeting.
• Support silicon bring-up, diagnosis, and physical failure analysis.
• Lead a multilocational team of DFT engineers.