PD Partition Lead (Physical Design, Semiconductors)

Capgemini Engineering is a global leader in engineering services, providing R&D and engineering support across industries such as autonomous cars and robotics. The company has nearly 60 years of experience, with over 420,000 team members worldwide, delivering technology and business transformation with AI and deep industry expertise.

• Good knowledge of synthesis flow, insertDFT scan/coverage, and optimization.
• Excellent skills in floorplan, power plan, CTS, place, route, and timing closure.
• Proficiency in scripting languages including Perl, TCL, and Python and knowledge of Makefile.
• Expertise in timing STA/PTSI, signal integrity closure, and ECO generation/implementation.
• Strong skills in EM/IR, DRC, LVS, ERC analysis and fixing.
• Experience in sign-off tape-out closure work.
• Partitioning experience is a plus.
• Experience in leading or tech leading small teams is a plus.

• Responsible for all aspects of Physical Design at full chip or block level in advanced technology nodes (10nm and below).
• Perform deep floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, scan re-ordering, placement, CTS, place and route.
• Manage timing analysis activities through sign-off, including signal integrity and noise, and execute ECO tasks (functional and timing).
• Lead validation and qualification tasks such as Formal Verification, EM/IR, DRC, LVS, Antenna, and ERC analysis and fixes.
• Contribute to the development and implementation of Low Power solutions.
• Develop and enhance timing scripts for clock skew analysis, critical path analysis, various IO interfaces, and constraints partitioning/budgeting.
• Complete multiple high complexity design cycles with little supervision.
• Possibility to lead other Physical Design Engineers.

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