PD Partition Lead (Physical Design, Semiconductors)

Capgemini Engineering is a global leader in engineering services with a team of engineers, scientists, and architects providing R&D and engineering services across industries including autonomous vehicles and robotics. Capgemini is an AI-powered global business and technology transformation partner with nearly 60 years of heritage and over 420,000 team members worldwide.

• Good knowledge of synthesis flow, insertDFT scan/coverage and optimization;
• Excellent floorplan, power plan, CTS, place, route, and timing closure skills;
• Proficiency using Perl/TCL/Python scripting and Makefile;
• Expertise in timing STA/PTSI – signal integrity closure, ECO generation/implementation skill;
• Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills;
• Experience with sign-off tape-out closure work;
• Partitioning experience is a plus;
• Experience in leading/tech leading small teams will be a plus.

• Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below);
• In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route;
• Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing);
• In charge with all validation/qualification tasks: Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes;
• Be part of the overall Low Power solution development and implementation;
• Develop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top-level to block level);
• Complete multiple design cycles of high complexity with little supervision;
• Possibility to lead other PD Engineers.

Capgemini is committed to diversity and inclusion, ensuring fairness in all employment practices.