Senior RTL Developer

Capgemini is an AI-powered global business and technology transformation partner with nearly 60 years of heritage and over 420,000 team members in more than 50 countries. They deliver end-to-end services and solutions across strategy, technology, design, engineering, and business operations, with a strong partner ecosystem.

• 7+ years of hands-on experience in digital design
• Strong knowledge of Verilog and/or VHDL
• Familiarity with SystemVerilog is a plus
• Experience with tools like Cadence Genus, Synopsys Design Compiler (DC), or Fusion Compiler is a plus
• Proven experience in RTL design, uArch development, and functional specs
• Deep understanding of linting tools, CDC methodologies, and debugging flows
• Familiarity with synthesis tools and SoC design is a strong plus
• Excellent communication and collaboration skills

• Lead Functional Specification Development for advanced digital systems
• Design and implement Microarchitecture (uArch) for high-performance blocks
• Perform RTL Debugging, ensuring design correctness and efficiency
• Run and analyze Lint Checks and CDC (Clock Domain Crossing) Checks
• Collaborate with verification, physical design, and architecture teams
• Contribute to Front-End Synthesis and optimization (Bonus)

Nice to have:

• Experience working on SoC-level integration and design
• Apply Power Optimization Techniques for energy-efficient designs

Capgemini is committed to diversity and inclusion, ensuring fairness in all employment practices and evaluating individuals based on qualifications and performance, not personal characteristics.