Senior DFT Engineer

The company provides end-to-end ASIC and COT design and turnkey manufacturing services to fabless companies and OEMs building advanced SoCs. Its offering covers architecture, RTL-to-GDSII implementation, analog/mixed-signal design, and productization through silicon, package, and test. Working across process nodes from 180nm to 2nm, it has completed over 350 tape-outs since 1986.

• BSc in Electrical Engineering from a recognized university
• Minimum 3 years of hands-on DFT experience; senior-level preferred
• Experience with scan, ATPG, at-speed test, memory BIST, I/O DFT methodologies
• Knowledge of scan insertion and ATPG for stuck-at, transition-delay, bridging and IDDQ fault models
• Experience with DFT DRC analysis and coverage debug using Synopsys DFT Compiler, TestMAX (TetraMAX), SpyGlass DFT, or Siemens (Mentor) Tessent tools
• Memory BIST experience with Tessent MBIST
• Strong knowledge of JTAG IEEE 1149.1, IEEE 1149.6, and IEEE 1500 standards
• Hands-on design and implementation of DFT features
• Gate-level simulation setup and runs for pattern validation
• Formal equivalence checking
• Scripting skills in Perl, Tcl, UNIX for flow automation

Nice to have:

• Broader Siemens Tessent experience (ScanPro, TestKompress, LBIST) beyond MBIST
• Advanced-node experience (7nm and below)
• Python scripting for flow automation

• Own Design-for-Test (DFT) end-to-end: concept through tape-out to production test hand-off
• Implement DFT features including scan insertion and ATPG
• Perform gate-level simulation setup and runs for pattern validation
• Conduct formal equivalence checking
• Automate flow using Perl, Tcl, and UNIX scripting