Senior Verification Engineer (UVM/SystemVerilog)

• At least 5 years of verification experience
• Proven ability to build verification environments from the ground up
• Experience with UVM and SystemVerilog
• Strong knowledge of Verification IPs and industry-standard protocols including PCIe, DDR, and AXI

Nice to have:

• Understanding of hardware-software interaction
• Experience with C, C++, Python, or SystemC

• Perform the full range of functional verification activities
• Develop verification environments from scratch, including drivers, monitors, scoreboards, and coverage models
• Integrate Verification IPs (VIPs) for protocols such as DDR, PCIe, and AXI
• Define and implement verification sequences for complex control-flow scenarios
• Gain a system-level understanding of products with strong hardware-software interaction
• Integrate and maintain reference models
• Define and execute test plans
• Establish verification methodologies, flows, and supporting infrastructure