Senior Analog Mixed-Signal Design Verification Engineer

• MS in Computer/Electrical Engineering.
• 5+ years of relevant industry experience.
• Hands-on experience in CMOS analog mixed-signal circuit design and verification.
• Experience modeling functional behavior of analog/mixed-signal circuits and systems using Verilog/SystemVerilog.
• Proficiency with EDA tools and environments such as Cadence Virtuoso for schematic creation and simulation.
• Proficiency with scripting/programming languages such as Python and MATLAB.
• Strong communication skills.

Nice to have:

• PhD in Computer/Electrical Engineering.
• Experience with AMS verification in advanced FinFET technology nodes.

• Define the co-simulation methodology and EDA infrastructure with analog and digital teams.
• Create Verilog/SystemVerilog test benches and behavioral models of analog and mixed-mode circuits.
• Develop methodologies for block- and chip-level mixed-mode verification.
• Support analog and digital teams during model bring-up and use.
• Perform AMS simulations.

• Candidates may be subject to verification and BGS screening as per applicable law.