Principal RFIC-PLL Design Engineer

Basic Qualifications:

• MS or PhD in Electrical Engineering or a related technical discipline.
• 10+ years of experience designing and developing high-speed (>20 GHz) PLLs and LOGEN for high-performance applications at RF and mmWave frequencies.
• Full proficiency in mixed-mode and RF modeling, simulation, and verification methodologies using tools such as MATLAB, Spectre, SystemVerilog, and AMS.
• Extensive experience in PLL silicon characterization and debugging.
• Strong background in fundamental analog/RF building blocks, including amplifiers, filters, and mixers.

Preferred Skills:

• Strong expertise in loop design for phase noise/jitter, spur profile, area, and power optimization.
• Extensive experience with analog building blocks such as LDOs, bias generators, and operational amplifiers.
• Fundamental understanding of device physics for process selection and performance optimization.
• Familiarity with digital design, digital verification, and SystemVerilog modeling.

Key Responsibilities:

• Lead the design, development, and integration of PLLs in advanced CMOS and SiGe technologies, focusing on performance optimization and trade-off analysis.
• Use Spectre and AMS flows to develop high-performance PLL circuits.
• Collaborate with RF system architects to define PLL and sub-block requirements from system specifications and support integration into RF payloads and terminals.
• Oversee layout, top-level integration, floorplanning, and verification for the overall design’s tape-out cycle.
• Work with validation and product engineers to develop test plans, facilitate bring-up, optimize performance, and support reliable, high-yield production cycles.
• Investigate and implement fundamental analog building blocks to enhance circuit performance, and mentor junior engineers in analog design practices.

• Candidates may be subject to verification and BGS screening as per applicable law.