Ideamotive

ASIC Physical Design Engineer (Back-End) | Senior/Lead

22k - 29k PLN22 000 - 29 000 PLN/ mies./ mies.UoPUmowa o pracę (brutto)

SeniorOn-site·WarsawFull-time·Umowa o pracę

#468881·Dodano 7 dni temu·0

Źródło: Ideamotive

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Tech Stack / Keywords

ASICCadence InnovusSynopsys IC Compiler IIFusion CompilerSTASynopsys PrimeTimeCadence TempusUPFCPFFD-SOI

Podsumowanie oferty

Lead the physical design of quantum-resistant cryptographic processors, from floorplanning through sign-off. You’ll take ownership of the physical design domain for a Polish deep-tech company developing post-quantum cryptography accelerators in silicon.

Wymagania

EU citizenship (strict formal requirement).
Minimum 5 years of commercial experience in ASIC back-end / physical design.
Proven track record of independently owning at least one tape-out from floorplan to sign-off.
Hands-on proficiency with Place & Route tools: Cadence Innovus or Synopsys IC Compiler II / Fusion Compiler.
Practical experience with STA analysis and sign-off using Synopsys PrimeTime or Cadence Tempus.
Familiarity with physical verification tools (DRC/LVS) such as Siemens Calibre, Synopsys IC Validator, or Cadence Pegasus.
Experience with low-power design methodologies and UPF or CPF standards.
Solid understanding of the full ASIC design flow and the front-end to back-end interface.
Degree in Electronics, Computer Engineering, or a related technical field.

Nice to have:

Experience with FD-SOI technology, specifically GlobalFoundries 22FDX.
Hands-on practice implementing Adaptive Body Bias (ABB).
Demonstrated success in power consumption optimization.
Knowledge of hardware security concepts: TRNG, PUF, and side-channel attack countermeasures.
Active security clearance (National, EU, or NATO).

Obowiązki

Lead the full physical implementation flow for quantum-resistant cryptographic processors.
Execute floorplanning, placement, clock tree synthesis (CTS), and routing.
Manage timing closure and STA sign-off across multiple corners and modes.
Own power planning, IR-drop analysis, and electromigration checks.
Design low-power architectures, including power domains, level shifters, isolation cells, and body bias distribution networks for Adaptive Body Bias (ABB).
Perform handoff to layout, implement ECOs, and prepare for tape-out in direct collaboration with the foundry.
Create technical documentation and support the chip certification process.

Benefity

Application of 50% tax-deductible costs (KUP) for creative/R&D work.
Employee Stock Option Plan (ESOP) for key engineering staff, launched upon conversion into a Joint-Stock Company.
Stable employment in a project with guaranteed multi-year funding.

Udziały pracownicze

Inne informacje

EU citizenship is a strict formal requirement.
Active security clearance (National, EU, or NATO) is listed as nice to have.

Ideamotive

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