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Senior Logic Design Engineer

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SeniorZdalnieFull-time

#469608·Dodano 14 dni temu·1

Źródło: Ciklum

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Tech Stack / Keywords

SystemVerilogFPGAASICRTLSTAAMD VersalAMD VivadoSynopsys VCSSiemens QuestaAXI

Podsumowanie oferty

Develop next-generation FPGA- and ASIC-based control platforms for systems supporting quantum computing. Design and optimize high-performance digital logic using SystemVerilog, with a focus on latency, timing, and resource constraints. Work with system architects, verification engineers, software developers, and hardware specialists on control and measurement systems.

Wymagania

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline, or equivalent practical experience.
4+ years of professional experience in FPGA or ASIC digital logic design.
Strong practical experience in RTL development using SystemVerilog (mandatory).
Solid understanding of digital logic design, computer architecture, and RTL microarchitecture.
Experience with logic synthesis, static timing analysis (STA), and timing optimization.
Practical experience with FPGA or ASIC design and implementation workflows.
Understanding of clock-domain crossing (CDC), synchronous digital design, and hardware interfaces.
Experience with simulation-based RTL verification and debugging.
Strong analytical, problem-solving, and communication skills.
English proficiency sufficient for effective collaboration within an international engineering team.

Nice to have:

Experience with AMD/Xilinx FPGA platforms, particularly AMD Versal.
Experience with AMD Vivado and related FPGA implementation tools.
Familiarity with Synopsys VCS, Siemens Questa, or equivalent simulation tools.
Experience with digital signal processing (DSP), waveform generation, or high-speed data acquisition.
Experience developing deterministic, ultra-low-latency digital systems.
Familiarity with AXI, PCIe, DDR, or other high-performance hardware interfaces.
Experience with ASIC-oriented RTL development and reusable digital IP.
Knowledge of Python, Tcl, or other languages used for development automation.
Experience with hardware-software co-design and embedded systems.
Experience in quantum computing, telecommunications, measurement equipment, or other performance-critical digital systems.

Obowiązki

Design and implement complex, configurable, low-latency RTL modules using SystemVerilog.
Develop digital logic for high-performance FPGA and ASIC applications, including signal processing, waveform generation, and real-time control.
Participate in the complete RTL development lifecycle, from architecture and microarchitecture definition to implementation and verification.
Optimize RTL designs for timing, latency, resource utilization, and power efficiency.
Perform logic synthesis, timing analysis, and optimization to meet design constraints.
Collaborate with verification engineers to ensure functional correctness and comprehensive test coverage.
Analyze system-level and software requirements and implement appropriate hardware-software interfaces.
Integrate proprietary digital IP into complex FPGA/ASIC architectures.
Participate in design reviews, debugging, and continuous improvement of engineering processes.

Benefity

Access to internal events, including meetups, conferences, and workshops.
Udemy access.
Language courses.
Company-paid certifications.
Company-paid premium medical package through Luxmed.
Access to the MyBenefit cafeteria platform.

Szkolenia wewnętrzne

Kursy językowe

Opieka zdrowotna

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