Ciklum

Expert Logic Design Engineer

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SeniorZdalnieFull-time

#469609·Dodano 14 dni temu·0

Źródło: Ciklum

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Tech Stack / Keywords

SystemVerilogFPGAASICRTLAMD/XilinxAMD VersalAMD VivadoSynopsys VCSSiemens QuestaAXI

Podsumowanie oferty

Lead the architecture, design, and optimization of high-performance FPGA and ASIC control platforms for systems used in quantum computing. Develop digital IP using SystemVerilog for advanced control and measurement systems.

Wymagania

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline, or equivalent practical experience.
6+ years of professional experience in complex FPGA or ASIC digital logic design.
Expert-level proficiency in SystemVerilog RTL design.
Extensive experience defining digital architectures and microarchitectures for complex hardware systems.
Proven experience independently delivering complex digital IP or subsystems from specification to implementation.
Deep understanding of RTL optimization, logic synthesis, static timing analysis (STA), and timing closure.
Experience optimizing digital designs for deterministic latency, high clock frequencies, resource utilization, and power efficiency.
Advanced knowledge of synchronous digital design, CDC, clocking architectures, and hardware interfaces.
Strong understanding of FPGA and/or ASIC development methodologies and implementation constraints.
Experience with simulation-based verification and debugging of complex digital systems.
Ability to evaluate architectural trade-offs, resolve technical issues, and guide implementation decisions.
Strong technical leadership, analytical, and communication skills.
English proficiency sufficient for effective collaboration within an international engineering team.

Nice to have:

Experience with AMD/Xilinx FPGA architectures, particularly AMD Versal.
Experience with AMD Vivado, FPGA implementation, and timing closure.
Familiarity with Synopsys VCS, Siemens Questa, and related verification and debugging tools.
Experience with ASIC digital IP development and FPGA-to-ASIC design considerations.
Experience designing DSP pipelines, waveform generation engines, or real-time control architectures.
Understanding of deterministic, nanosecond-scale timing and synchronization.
Experience with high-speed interfaces such as AXI, PCIe, DDR, or proprietary interconnects.
Experience with performance, area, and power (PPA) optimization.
Knowledge of Python, Tcl, or other languages used for EDA workflow automation.
Experience leading technical design reviews or mentoring senior engineers.
Background in quantum computing, semiconductor development, telecommunications, high-performance instrumentation, or similar technology domains.

Obowiązki

Lead architecture, microarchitecture, and RTL implementation of complex, high-performance FPGA/ASIC digital subsystems.
Design and optimize configurable, ultra-low-latency digital logic using SystemVerilog.
Drive digital IP development from system requirements and architectural trade-offs through RTL implementation and integration.
Make architectural decisions to optimize timing performance, latency, resource utilization, scalability, and power efficiency.
Address timing closure, clock-domain crossing, synchronization, and critical-path optimization.
Develop digital processing and control architectures, including signal-processing pipelines, waveform generation, and deterministic real-time control.
Define hardware-software interfaces and collaborate with software and system architecture teams on system integration.
Collaborate with verification engineers to define verification strategies and ensure functional coverage.
Review RTL designs, identify architectural and implementation risks, and provide technical guidance to other engineers.
Contribute to FPGA platforms and reusable digital IP for future ASIC implementations.
Drive engineering best practices, design quality, and technical improvements across the development lifecycle.

Benefity

Access to internal meetups, conferences, workshops, Udemy, language courses, and company-paid certifications.
Company-paid premium medical package through Luxmed.
Access to the MyBenefit cafeteria platform to choose perks.

Kursy językowe

Opieka zdrowotna

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