Senior Logic Design Engineer (FPGA/ASIC)

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MidZdalnie·Remote PolandInne·B2B

#470437·Dodano 6 dni temu·1

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Tech Stack / Keywords

FPGA/ASIC digital logic designSystemVerilogSTA, timing optimizationRTL debugging

Podsumowanie oferty

Develop high-performance FPGA/ASIC digital logic for advanced quantum computing control and measurement technology. Design configurable, low-latency hardware in a hands-on R&D role using SystemVerilog.

Wymagania

4+ years of professional FPGA/ASIC digital logic design experience.
Strong hands-on SystemVerilog RTL development.
Solid understanding of digital microarchitecture and synchronous design.
Experience with synthesis, STA, timing optimization and CDC.
Practical FPGA/ASIC implementation and RTL debugging experience.
Confident English (B2+).

Nice to have:

AMD/Xilinx Versal, Vivado, Questa/VCS, DSP, high-speed interfaces, ASIC IP, Python/Tcl automation and hardware-software co-design.

Obowiązki

Design and implement complex SystemVerilog RTL modules.
Develop signal processing, waveform generation and real-time control logic.
Contribute to architecture, microarchitecture and RTL integration.
Perform synthesis, static timing analysis and optimization.
Debug and verify RTL functionality with verification teams.
Integrate digital IP and hardware-software interfaces.

Inne informacje

The listed locations are Ukraine, Poland, Czech Republic, Romania, Slovakia and Spain.

DCV Technologies

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